An electronic computer aided design (“E-CAD”) package is utilized to construct a Very Large Scale Integration (“VLSI”) circuit design. Generally, the VLSI circuit design is the full electronic description of an electronic part (e.g., an integrated circuit). The VLSI circuit design is typically divided into functional areas, each known as a functional unit block (“FUB”). Each FUB is constructed from one or more hierarchical design blocks (‘cells’) that provide specific functionality to the FUB. Cells may be constructed from electronic design elements (e.g., nets, resistors, transistors, etc.) and other cells, and may be used one or more times within the VLSI circuit design. A cell that includes components (and not merely other cells) is known as a ‘leaf’ cell.
The VLSI circuit design includes a layout that defines physical layers of the integrated circuit constructed using a fabrication process with defined parameters and rules. Generally, this VLSI circuit design layout means the artwork, mask or physical representation of the electronic part; and the fabrication process means the process by which the electronic part is manufactured. In one example, the fabrication process defines a minimum track width and minimum transistor size. Typically, the fabrication process utilizes a grid with a predefined pitch upon which the layout is constructed.
The layout of a VLSI circuit design is an engineering-intensive process. By way of example, a multitude of design engineers typically collaborate on a VLSI circuit design that includes one poly-silicon layer (poly layer), for components (transistors, capacitors, etc.), and one or more metal layers (metal 1, metal 2, metal 3, etc.), which provide electrical connectivity to the components.
Improvements in the fabrication process result in decreased pitch, thereby increasing density of components of the poly layer. It is therefore often desirable to utilize any available improvements in the fabrication process. To take advantage of the improvements, design engineers often incorporate a ‘shrink’ process to reduce the layout by a proportional amount. However, a layout generated with a shrink process does not incorporate additional design rules (e.g., constraints) introduced by the new fabrication process. Accordingly, the shrunk layout is initially unusable and the circuit design layout is usually re-engineered to ensure conformity to the design rules and constraints of the new fabrication process. Often the entire layout is re-engineered to achieve conformity to the design rules.
Generally, therefore, the term “shrink” means the engineering effort of reducing one VLSI design to another, smaller VLSI design that is based upon a fabrication process with design rules that allow a more dense VLSI circuit design layout. The afore-mentioned design rules generally mean the rules embodied by the VLSI circuit design layout so that the electronic part may be manufactured by the fabrication process. An exemplary design rule is that transistors cannot be rotated. An exemplary constraint is that a net cannot incorporate forty-five degree angles.
If the VLSI circuit design has billions of design elements, re-engineering associated with a shrink process can take many man-months to complete. Opportunities to utilize improved fabrication processes are therefore often ignored due to development costs.